In an aspect of conventional packaging technologies, such as wafer level packaging (WLP), an interconnect structure, including redistribution layers (RDLs), may be formed over a die and electrically connected to active devices in a die. An advantageous feature of this packaging technology is the possibility of forming a fan-out interconnect structure. For example, I/O pads on a die can be redistributed to a greater area than the die, and hence the number of I/O pads packed on the surfaces of the dies can be increased.
In such packaging technologies, a molding compound may be formed around the die to provide extra surface area for supporting the fan-out interconnect structure. RDLs of the interconnect structure electrically connect I/O pads on the die to the external I/O pads on the fan-out interconnect structure. The external I/O pads may be disposed over both the die and the molding compound.